This present invention relates to chemical mechanical polishing apparatus and methods.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization is needed to planarize the substrate surface for photolithography.
Chemical mechanical polishing (CMP) by a polisher is one accepted method of planarization. A conventional polisher includes a base with several polishing stations and a loading port. The loading port is typically dedicated to providing a precise position for chucking by a carrier or polishing head. After chucking the substrate from the loading port, the polisher may move the substrate to one or more of the polishing stations for processing. During planarization, the exposed surface of the substrate is placed against a polishing surface of a polishing pad, such as a rotating polishing disk or linearly advancing belt. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, which can include abrasive particles, is supplied to the surface of the polishing pad, and the relative motion between the substrate and polishing pad results in planarization and polishing.
Conventional polishing pads include “standard” pads and fixed-abrasive pads. A typical standard pad has a polyurethane polishing layer with a durable roughened surface, and can also include a compressible backing layer. In contrast, a fixed-abrasive pad has abrasive particles held in a containment media, and can be supported on a generally incompressible backing layer.
Overall, the process of forming an integrated circuit can be prohibitively and increasingly expensive. One major factor in expense is the necessary size of a conventional semiconductor fabrication plant that includes numerous processing machines other than the polisher. Each of the machines consume a certain area of the floor, known as a footprint. In particular, the loading port of a polisher can consume up to a quarter of a polisher footprint. Another major factor in expense is the amount time needed for the numerous steps in processing. Time of processing affects throughput, or production volume. Moreover, many steps require a handoff which can spoil a substrate through damage.